For some Electronics students a bare metal FPGA can be quite boring, knowing that a Microcontroller can do a lot better job in many situation. However, that doesn't mean that FPGA is boring itself! For instance, we can store an information about an imagine inside the Memory of FPGA and then put the image through the VGA cable onto the LCD display.
For more info and to download source code: https://www.pantechsolutions.net/cpld-fpga-boards/spartan3.
First things first, for the project I used Diligent Basys 2 board, which now is almost obsolete. I suggest you using some newer FPGA for a better image quality, larger number of connections and larger amount of memory as the image that I put here used up about 99% of the chip!
I used Verilog programming language and one of the software packages from Xilinx (Any other should do the job as well). Digilent Adept 2 software was used to upload the bit file from Verilog to the board.
One more interesting thing to point out - you probably noticed how distorted the image on the screen is. This is because the board is really old and it uses an awful clock! I currently don't have an external clock, which can be put instead, but if you have one (or have a newer board), you will most likely get rid of this effect.
More about the board:
Title | color_maker-s3esk (simple VGA tester) |
Author | Nikolaos Kavvadias (C) 2014, 2015, 2016 |
Contact | [email protected] |
Source | Mike Field (for the VGA controller; see AUTHORS) |
Website | http://www.nkavvadias.com |
Release Date | 08 August 2016 |
Version | 1.1.1 |
Rev. history | |
v1.1.1 | 2016-08-08 Added clean-up script. |
v1.1.0 | 2016-07-10 GHDL simulation scripts and generation of log file forVGA simulation. |
v1.0.2 | 2016-07-10 Update for 2016. |
v1.0.1 | 2014-06-18 Changed README to README.rst; COPYING to LICENSE. |
v1.0.0 | 2014-06-09 Initial release for the Spartan-3E Starter kit board. |
1. Introduction
color_maker
is a simple design for testing VGA output. This version of thecolor_maker
produces 3-bit RGB color (R1G1B1) as supported by the XilinxSpartan-3E starter kit board. 3 out of the 4 available slide switches(specifically switches SW2, SW1, SW0) are used for setting a specific colorout of the eight unique colors that are available.The following table summarizes the available colors.
R | G | B | Description |
---|---|---|---|
0 | 0 | 0 | Black (Noir) |
0 | 0 | 1 | Blue |
0 | 1 | 0 | Green |
0 | 1 | 1 | Cyan |
1 | 0 | 0 | Red |
1 | 0 | 1 | Magenta |
1 | 1 | 0 | Yellow |
1 | 1 | 1 | White |
For the standard VGA resolution (640x480@60Hz), a 25MHz clock is used, asproduced by the
clockdiv
clock divider (divide by 2). The VGA controlleris implemented by vgactrl.vhd
. The color selection logic is verysimple and directly assigns SW2 to the R, SW1 to G and SW0 to the B component.For 800x600@72Hz, a 50 MHz clock should be used.The
vga_controller
design has been adapted from the work by Mike Field:http://hamsterworks.co.nz/mediawiki/index.php/Hidef_snow2. File listing
The
color_maker
distribution includes the following files:/color_maker-s3esk | Top-level directory |
AUTHORS | List of authors. |
LICENSE | 3-clause modified BSD license. |
README.rst | This file. |
README.html | HTML version of README.rst. |
README.pdf | PDF version of README.rst. |
clean.sh | A bash script for cleaning simulation artifacts. |
clockdiv.vhd | Configurable, portable, clock divider. |
color_maker.vhd | Color assignment logic. |
color_maker_top.ucf | User Constraints File for the XC3S500E-FG320-4device. |
color_maker_top.vhd | The top-level RTL VHDL design file. |
color_maker_top_tb.vhd | Testbench for the top-level RTL VHDL design file. |
color_maker_top-syn.sh | Bash shell script for synthesizing thecolor_maker design with Xilinx ISE. |
ghdl.mk | Makefile for VHDL simulation with GHDL. |
ghdl.sh | Bash shell script for running the simulation withGHDL. |
impact_s3esk.bat | Windows Batch file for automatically invoking XilinxIMPACT in order to download the generated bitstreamto the target hardware. |
rst2docs.sh | Bash script for generating the HTML and PDF versions. |
vgactrl.vhd | RTL VHDL code for the VGA controller. |
xst.mk | Standard Makefile for command-line usage of ISE. |
3. Usage
The
color_maker
distribution includes scripts for logic synthesis automationsupporting Xilinx ISE. The corresponding synthesis script can be edited in orderto specify the following for adapting to the user's setup:XDIR
: the path to the/bin
subdirectory of the Xilinx ISE/XSTinstallation where thexst.exe
executable is placedarch
: specific FPGA architecture (device family) to be used for synthesispart
: specific FPGA part (device) to be used for synthesis
![Display Display](http://codehackcreate.com/wp-content/uploads/2018/06/F18A_MK2_REV_F-iso.png)
3.1. Running the simulation script
This step assumes that the GHDL executable is in the user's
$PATH
, e.g., byusing:Then the simulation shell script can be run from a UNIX/Linux/Cygwin command line:
![Vga Vga](/uploads/1/2/4/8/124867954/824929658.png)
This will produce a text file named
color_maker_top_results.txt
with the valuesof current time whenever a clock event occurs (as integer) and the signals hs
,vs
, red
, green
and blue
(as binary). This can be used by an externaltool, the VGA simulator (http://ericeastwood.com/lab/vga-simulator/) for visualizingthe outcome if a VGA/CRT monitor would be driven. A downloadable version of theVGA simulator also exists: https://github.com/MadLittleMods/vga-simulatorIn order to work with the VGA simulator without further changes, the red, green andblue signals are extended to 3, 3, and 2 bits, respectively in the testbench.
To clean up simulation artifacts, including the generated diagnostics file, usethe
clean.sh
script:3.2. Running the synthesis script
For running the Xilinx ISE synthesis tool, generating FPGA configurationbistream and downloading to the target device, execute the corresponding scriptfrom within the
color_maker-s3esk
directory:In order to successfully run the entire process, you should have the targetboard connected to the host and it should be powered on.
The synthesis procedure invokes several Xilinx ISE command-line tools for logicsynthesis as described in the corresponding Makefile, found in thethe
color_maker-s3esk
directory.Typically, this process includes the following:
- Generation of the
*.xst
synthesis script file. - Generation of the
*.ngc
gate-level netlist file in NGC format. - Building the corresponding
*.ngd
file. - Performing mapping using
map
which generates the corresponding*.ncd
file. - Place-and-routing using
par
which updates the corresponding*.ncd
file. - Tracing critical paths using
trce
for reoptimizing the*.ncd
file. - Bitstream generation (
*.bit
) usingbitgen
, however with unused pins.
As a result of this process, the
color_maker_top.bit
bitstream file isproduced.Then, the shell script invokes the Xilinx IMPACT tool by a Windows batch file,automatically passing a series of commands that are necessary for configuringthe target FPGA device:
- Set mode to binary scan.
- Set cable port detection to auto (tests various ports).
- Identify parts and their order in the scan chain.
- Assign the bitstream to the first part in the scan chain.
- Program the selected device.
- Exit IMPACT.
4. Prerequisites
- [suggested] Linux (e.g., Ubuntu 16.04 LTS) or MinGW environment on Windows 7 (64-bit).
- [suggested] GHDL simulator: http://ghdl.free.frThe 0.33 version on Linux Ubuntu 16.04 LTS was used.
- [optional] The VGA simulator: http://ericeastwood.com/lab/vga-simulator/
- Xilinx ISE (free ISE webpack is available from the Xilinx website):http://www.xilinx.com.The 14.6 version on Windows 7/64-bit is known to work.